1. Field of the Invention
This invention relates generally to wireless packaging for an integrated circuit chip and, more particularly, to wireless packaging for an MMIC chip that includes providing RF and DC via feedthroughs extending into the chip from top circuit layer to backside of the chip to directly connect RF and DC inputs and outputs to microstrips and traces formed on a substrate positioned relative to the backside of the chip.
2. Discussion of the Related Art
Millimeter-wave and/or microwave integrated circuit (MMIC) chips are used in many types of electrical systems that transfer signals at millimeter-wave and microwave frequencies. The millimeter-wave or microwave electrical systems will generally include one or more MMIC chips packaged within a suitable housing. Substrates are positioned within the housing to support microstrips and the like to provide RF connections between the MMIC chips and provide DC power input connections to the chips. The high frequency signals at these wavelengths require specialized RF and DC input and output connections to the chip suitable for state-of-the-art MMIC assembly technology and to minimize losses in a cost effective manner.
In one MMIC chip packaging design, the RF inputs and outputs and DC power inputs to the MMIC chip employ ribbonbond and wirebond connections to connect the chip to the microstrips on the substrates. FIG. 1 shows a top plan view of a conventional MMIC chip 10 employing these types of electrical connections. The MMIC chip 10 is mounted at its backside within a cavity 12 of a packaging fixture 14 by a suitable conductive epoxy, solder or the like to position and protect the chip 10. The fixture 14 can be made of any suitable conductive material, such as an aluminum or brass, and is generally maintained at a reference potential, such as ground. The chip 10 includes a backside metal layer 16 acting as a ground plane that covers the entire back surface of the chip 10. The epoxy or solder connection between the metal layer 16 and the fixture 14 provides the common reference potential connection to the chip 10. In alternate designs, the backside metal layer 16 can be at a bias potential, free floating, etc. An electrical layout section 18 is formed on GaAs substrate and includes the electrical components associated with the MMIC chip 10 depending on the particular application. In this plan view, the size of the layer 16 is shown exaggerated relative to the layout section 18 to better depict the input and output connections to the chip 10 that will be discussed below.
The chip 10 includes a plurality of ground vias 20 that extend through the chip 10 and are connected to the layer 16 to allow the electrical components within the section 18 of the chip 10 to be connected to the common reference potential. A plurality of DC pads 22 are mounted on top of the chip 10 and are electrically connected to conductive traces 24 that extend into the fixture 14 by wirebonds 26. The DC pads 22 are appropriately connected to the components in the section 18 to provide DC voltage potentials to be applied to the components within the chip 10. Microstrips 28 are patterned on non-conductive substrates 30 positioned within the fixture 14 to transfer the high frequency RF microwave or millimeterwave signals to and from the chip 10. The substrates 30 extend through the fixture 14 into the cavity 12, as shown. Ribbonbonds 32 are electrically connected to the microstrips 28 and to conductive pads 34 on top of the chip 10. The pads 34 are electrically connected to microstrip lines 36 on the chip 10 to transmit the high frequency RF signals to the electrical components in the section 18. The ground vias 20 that are provided adjacent to the pads 34 allow for on-wafer measurement capabilities, or for co-planar connection applications, as is well understood in the art. The ribbonbonds 32 generally have a bowed configuration to provide play for thermal and mechanical stresses. In this design, the substrates 30 are at the same level as the chip 10 such that the microstrips 28 are substantially parallel with the top surface of the chip 10, so that the wirebonds 26 and the ribbonbonds 32 provide the electrical connections to the top of the chip 10 in an efficient manner.
The connection technique using the wirebonds 26 and the ribbonbonds 32 for the design discussed above, has a number of drawbacks. Particularly, this technique is somewhat labor intensive in that it requires an operator to carefully make the wirebond and ribbonbond connections. Additionally, the ribbonbond connections to the MMIC chip 10 degrade the chip performance because the ribbonbonds 32 add a finite inductance in series with the MMIC chip 10. This ribbonbond inductance degrades performance, which is most noticeable at microwave and millimeterwave frequencies. It is known in the art that the inductance generated by each ribbonbond 32 can be using an off-chip matching network (not shown) that includes an open circuit stub matching network that negates the inductance of the ribbonbonds 32, and produces a low pass filter network that prevents the inductive reactance from degrading circuit performance. However, this method of inductance compensation is time consuming to implement, and requires separate substrate designs depending on the length and the thickness of the connecting ribbon.
Other methods of providing RF inputs and outputs to an MMIC chip are known in the art that do not use ribbonbonds. One method is generally referred to as flip-chip circuit technology, and employs a wireless connection to the MMIC chip. In flip-chip circuit technology, the face (top) of the processed MMIC chip 10 is soldered or epoxied to a connecting substrate instead of the backside metal layer. Referring to FIG. 1, in the flip-chip design, the chip 10 would be flipped over, and various connection points in the electrical layout section 18 would be electrically connected to solder bumps or the like formed on traces on a mounting substrate to provide the appropriate connections to the chip 10.
Flip-chip circuit technology, however, also has several disadvantages. These disadvantages include trapping heat between the MMIC chip and the mounting substrate because the MMIC chip surface cannot take advantage of heat convection from air circulation. Additionally, the MMIC chip cannot be visually inspected for failure mechanisms after the MMIC chip is mounted on the substrate because the face of the chip is covered by the mounting substrate, and the electrical connections between the MMIC chip and the substrate cannot be checked because the connections are not exposed. Also, the circuit design has to be in coplanar technology. Coplanar technology has notable disadvantages at microwave frequencies: heat dissipation, chip size, and allows only for low level circuit complexity. Further, when the chip is flipped over and mounted to the substrate, the circuit performance changes from when the chip was tested when right side up.
Thus, there is a need for a wireless MMIC chip interconnection process which allows heat dissipation and troubleshooting of the installed MMIC chip. It is therefore an object of the present invention to provide such a wireless MMIC chip packaging scheme for MMIC microstrip circuits.